The method we follow is based on the FER(FPGA Empirical Roofline) tool
(doi:10.3233/APC200085), developed within the EuroExa project (https://euroexa.eu/),
and avaible on GitHub (https://baltig.infn.it/EuroEXA/FER).

- Set the number of FLOP editing the FLOP_ELEM macro in "parameters.h"

- $ make HLS
  The FER is compile to the step HLS

- $ make bitstream
  The bitstream is generated

- $ make energy
  Only the host code of the FER is compiled. The resulting executable calls 100
  times the accelerator, allowing in the meantime power measurements.
  A valid bitstream should be already available.